clk_hw_register_divider
hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
hw = clk_hw_register_divider(NULL, clk_name, parent_name,
hw = clk_hw_register_divider(NULL, div_data->name,
clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
hws[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
hws[IMX6SLL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
hws[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],
return clk_hw_register_divider(NULL, name, parent, 0,
return clk_hw_register_divider(NULL, name, parent, flags,
hw = clk_hw_register_divider(dev, mcd->name, mcd->parent_name,
clk_hw = clk_hw_register_divider(dev, core->name,
clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
clk_hw = clk_hw_register_divider(ctx->dev, list->name,