clk_gen
uint64_t clk_gen:1;
uint64_t clk_gen:1;
uint64_t clk_gen:1;
uint64_t clk_gen:1;
uint64_t clk_gen:1;
uint64_t clk_gen:1;
u32 clk_gen;
u32 clk_gen; /* divider for spi output clock generated by the controller */
mpfs_spi_write(spi, REG_CLK_GEN, spi->clk_gen);
unsigned long clk_hz, spi_hz, clk_gen;
clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) {
clk_gen = DIV_ROUND_UP(clk_hz, spi_hz);
clk_gen = fls(clk_gen) - 1;
if (clk_gen > CLK_GEN_MODE0_MAX)
spi->clk_gen = clk_gen;
const struct cs43130_clk_gen *clk_gen;
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
if (!clk_gen)
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>