clear_irq
u64 clear_irq;
for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
void (*clear_irq)(struct exynos_adc *info);
.clear_irq = exynos_adc_v1_clear_irq,
.clear_irq = exynos_adc_v1_clear_irq,
.clear_irq = exynos_adc_v1_clear_irq,
.clear_irq = exynos_adc_v1_clear_irq,
.clear_irq = exynos_adc_v2_clear_irq,
.clear_irq = exynos_adc_v2_clear_irq,
.clear_irq = exynos_adc_v2_clear_irq,
if (info->data->clear_irq)
info->data->clear_irq(info);
ams_info.clear_irq(irqs_to_clear);
ams_info.clear_irq = ams_i2c_clear_irq;
ams_info.clear_irq = ams_pmu_clear_irq;
void (*clear_irq)(enum ams_irq reg);
clear_irq(bus, oldirq);
void (*clear_irq)(void);
int clear_irq, i;
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
clear_irq = NAU8824_KEY_RELEASE_IRQ;
if (!clear_irq)
clear_irq = active_irq;
regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
int active_irq, clear_irq, i;
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
NAU8824_REG_CLEAR_INT_REG, clear_irq);
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
clear_irq = NAU8824_JACK_EJECTION_DETECTED;
int active_irq, clear_irq, i;
clear_irq = (0x1 << i);
if (active_irq & clear_irq)
NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
int active_irq, clear_irq = 0, event = 0, event_mask = 0;
clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
clear_irq = NAU8825_KEY_RELEASE_IRQ;
clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
if (!clear_irq)
clear_irq = active_irq;
regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);