chv3_i2s_wr
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0);
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0);
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT);
chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1);
chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1);
chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT);
chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr);
chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes);
chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1);
chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1);
chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx);
chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx);