CAS_BASE
val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
val = CAS_BASE(RX_PAUSE_THRESH_OFF,
val |= CAS_BASE(RX_PAUSE_THRESH_ON,
val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
val = CAS_BASE(RX_PAGE_SIZE, val);
val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
CAS_BASE(RX_INDEX_RING, 0));
cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
CAS_BASE(RX_INDEX_RING, ring));
ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);