channel_writel
channel_writel(atchan, CFG, cfg);
channel_writel(atchan, SADDR, 0);
channel_writel(atchan, DADDR, 0);
channel_writel(atchan, CTRLA, 0);
channel_writel(atchan, CTRLB, 0);
channel_writel(atchan, DSCR, atchan->save_dscr);
channel_writel(atchan, CFG, atchan->save_cfg);
channel_writel(atchan, SADDR, 0);
channel_writel(atchan, DADDR, 0);
channel_writel(atchan, CTRLA, 0);
channel_writel(atchan, CTRLB, 0);
channel_writel(atchan, DSCR, desc->sg[0].lli_phys);
channel_writel(atchan, SPIP,
channel_writel(atchan, DPIP,
channel_writel(dwc, SAR, lli_read(desc, sar));
channel_writel(dwc, DAR, lli_read(desc, dar));
channel_writel(dwc, CTL_LO, ctllo);
channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
channel_writel(dwc, LLP, first->txd.phys | lms);
channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
channel_writel(dwc, CTL_HI, 0);
channel_writel(dwc, CFG_LO, cfglo);
channel_writel(dwc, CFG_HI, cfghi);
channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
channel_writel(dwc, CFG_LO, cfglo);
channel_writel(dwc, CFG_HI, cfghi);
channel_writel(dwc, CFG_LO, cfglo);
channel_writel(dwc, CFG_HI, cfghi);
channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
channel_writel(idma64c, CFG_LO, cfglo);
channel_writel(idma64c, CFG_HI, cfghi);
channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
channel_writel(pd_chan, SIZE, desc->regs.size);
channel_writel(pd_chan, NEXT, desc->regs.next);
channel_writel(pd_chan, NEXT, desc->txd.phys);
channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
channel_writel(dc, CHAR, 0);
channel_writel(dc, SAR, 0);
channel_writel(dc, DAR, 0);
channel_writel(dc, CNTR, 0);
channel_writel(dc, SAIR, 0);
channel_writel(dc, DAIR, 0);
channel_writel(dc, CCR, 0);
channel_writel(dc, CSR, errors);