channel_readl
atchan->save_dscr = channel_readl(atchan, DSCR);
atchan->save_cfg = channel_readl(atchan, CFG);
channel_readl(atchan, SADDR),
channel_readl(atchan, DADDR),
channel_readl(atchan, CTRLA),
channel_readl(atchan, CTRLB),
channel_readl(atchan, CFG),
channel_readl(atchan, DSCR));
dscr = channel_readl(atchan, DSCR);
ctrla = channel_readl(atchan, CTRLA);
new_dscr = channel_readl(atchan, DSCR);
ctrla = channel_readl(atchan, CTRLA);
ctrla = channel_readl(atchan, CTRLA);
channel_readl(dwc, SAR),
channel_readl(dwc, DAR),
channel_readl(dwc, LLP),
channel_readl(dwc, CTL_HI),
channel_readl(dwc, CTL_LO));
u32 ctlhi = channel_readl(dwc, CTL_HI);
u32 ctllo = channel_readl(dwc, CTL_LO);
llp = channel_readl(dwc, LLP);
while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
u32 cfglo = channel_readl(dwc, CFG_LO);
u32 cfglo = channel_readl(dwc, CFG_LO);
u32 cfglo = channel_readl(dwc, CFG_LO);
u32 cfglo = channel_readl(dwc, CFG_LO);
u32 ctlhi = channel_readl(idma64c, CTL_HI);
cfglo = channel_readl(idma64c, CFG_LO);
cfglo = channel_readl(idma64c, CFG_LO);
cfglo = channel_readl(idma64c, CFG_LO);
pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
csr = channel_readl(dc, CSR);
channel_readl(dc, CSR));
csr = channel_readl(dc, CSR);
if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {