cgx_write
cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg);
cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
cgx_write(cgx_dev, lmac_id, offset, val);
cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F));
cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx, 0,
cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
cgx_write(cgx, 0,
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
cgx_write(cgx, 0,
cgx_write(cgx, lmac_id,
cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0);
cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val);
cgx_write(rpm, lmac, offset, val);