cgs_read_register
acp_mode = cgs_read_register(cgs_device,
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
value = cgs_read_register(ctx->cgs_device, address);
cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);
cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
(cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
cgs_read_register(hwmgr->device, mmDLL_CNTL);
cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
cgs_read_register(hwmgr->device, mmMPLL_SS1);
cgs_read_register(hwmgr->device, mmMPLL_SS2);
mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
data = cgs_read_register(hwmgr->device, config_regs->offset);
value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
cur_value = cgs_read_register(hwmgr->device, index);
cur_value = cgs_read_register(hwmgr->device,
PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
cgs_read_register(device, mm##reg), reg, field, fieldval))
data = cgs_read_register(hwmgr->device, config_regs->offset);
((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
return cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
*value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
(cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
tmp = cgs_read_register(hwmgr->device,
tmp = cgs_read_register(hwmgr->device,
return cgs_read_register(hwmgr->device,
hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
uint32_t val = cgs_read_register(hwmgr->device,
((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
temp_reg = cgs_read_register(hwmgr->device,
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &