cgs_device
int amd_acp_hw_init(struct cgs_device *cgs_device,
acp_mode = cgs_read_register(cgs_device,
int amd_acp_hw_init(struct cgs_device *cgs_device,
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
adev->acp.cgs_device =
if (!adev->acp.cgs_device)
if (adev->acp.cgs_device)
amdgpu_cgs_destroy_device(adev->acp.cgs_device);
r = amd_acp_hw_init(adev->acp.cgs_device,
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
struct cgs_device *cgs_device;
static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
id = fw_type_convert(cgs_device, type);
info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
struct cgs_device base;
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
struct amdgpu_cgs_device *cgs_device = kmalloc_obj(*cgs_device);
if (!cgs_device) {
cgs_device->base.ops = &amdgpu_cgs_ops;
((struct amdgpu_cgs_device *)cgs_device)->adev
cgs_device->adev = adev;
return (struct cgs_device *)cgs_device;
void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
kfree(cgs_device);
static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned int offset)
static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned int offset,
static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
cgs_write_register(ctx->cgs_device, address, value);
value = cgs_read_register(ctx->cgs_device, address);
cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all);
cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8);
init_data.cgs_device = adev->dm.cgs_device;
if (adev->dm.cgs_device) {
amdgpu_cgs_destroy_device(adev->dm.cgs_device);
adev->dm.cgs_device = NULL;
adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
if (!adev->dm.cgs_device) {
struct cgs_device *cgs_device;
dc_ctx->cgs_device = init_params->cgs_device;
struct cgs_device *cgs_device;
void *cgs_device;
return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
(((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
struct cgs_device;
typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,