cfg_bits
writel(cfg_bits, ctx->base + layer_offset);
layer_reg_wr(struct dpu_context *ctx, u32 offset, u32 cfg_bits, int index)
static const int cfg_bits[3] = { 1<<12, 1<<14, 1<<13 };
snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, cfg_bits[idx]);
ac97->spec.ad18xx.chained[idx] = cfg_bits[idx];