cf_port
struct octeon_cf_port *cf_port = ap->private_data;
octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
if (cf_port->is_true_ide)
octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
if (cf_port->is_true_ide)
cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
struct octeon_cf_port *cf_port = ap->private_data;
c = (cf_port->dma_base & 8) >> 3;
cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
struct octeon_cf_port *cf_port;
cf_port = ap->private_data;
cf_port->dma_finished = 0;
struct octeon_cf_port *cf_port = qc->ap->private_data;
cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
struct octeon_cf_port *cf_port = ap->private_data;
dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
struct octeon_cf_port *cf_port;
cf_port = ap->private_data;
dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
cf_port->dma_finished = 1;
if (!cf_port->dma_finished)
cvmx_write_csr(cf_port->dma_base + DMA_INT,
hrtimer_start_range_ns(&cf_port->delayed_finish,
struct octeon_cf_port *cf_port = container_of(hrt,
struct ata_port *ap = cf_port->ap;
if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
struct octeon_cf_port *cf_port;
cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
if (!cf_port)
cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
cf_port->cs0 = upper_32_bits(reg);
if (cf_port->is_true_ide) {
cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
if (!cf_port->dma_base) {
cf_port->cs1 = upper_32_bits(reg);
ap->private_data = cf_port;
pdev->dev.platform_data = cf_port;
cf_port->ap = ap;
} else if (cf_port->is_true_ide) {
hrtimer_setup(&cf_port->delayed_finish, octeon_cf_delayed_finish, CLOCK_MONOTONIC,
cf_port->c0 = ap->ioaddr.ctl_addr;
cf_port->is_true_ide ? ", True IDE" : "");
struct octeon_cf_port *cf_port = dev_get_platdata(dev);
if (cf_port->dma_base) {
cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
__raw_writeb(0, cf_port->c0);
__raw_writeb(ATA_SRST, cf_port->c0);
__raw_writeb(0, cf_port->c0);
conf.cf_port =
conf.cf_port =