drivers/gpu/drm/bridge/sii9234.c

354

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);

drivers/gpu/drm/bridge/sii9234.c

355

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,

drivers/gpu/drm/bridge/sii9234.c

357

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,

drivers/gpu/drm/bridge/sii9234.c

359

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);

drivers/gpu/drm/bridge/sii9234.c

360

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);

drivers/gpu/drm/bridge/sii9234.c

361

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,

drivers/gpu/drm/bridge/sii9234.c

363

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,

drivers/gpu/drm/bridge/sii9234.c

365

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,

drivers/gpu/drm/bridge/sii9234.c

367

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);

drivers/gpu/drm/bridge/sii9234.c

368

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,

drivers/gpu/drm/bridge/sii9234.c

371

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);

drivers/gpu/drm/bridge/sii9234.c

372

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);

drivers/gpu/drm/bridge/sii9234.c

373

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,

drivers/gpu/drm/bridge/sii9234.c

375

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,

drivers/gpu/drm/bridge/sii9234.c

377

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);