cec_read
.read = cec_read,
u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
cec_read(priv, REG_CEC_RXSHPDINT);
int val = cec_read(priv, REG_CEC_ENAMODS);
val = cec_read(priv, REG_CEC_DES_FREQ2);
sta = cec_read(priv, REG_CEC_INTSTATUS);
cec = cec_read(priv, REG_CEC_RXSHPDINT);
lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
mask = cec_read(cec, TEGRA_CEC_INT_MASK);
v = cec_read(cec, TEGRA_CEC_RX_REGISTER);
u32 state = cec_read(cec, TEGRA_CEC_HW_CONTROL);
u32 reg = cec_read(cec, TEGRA_CEC_HW_CONTROL);
mask = cec_read(cec, TEGRA_CEC_INT_MASK);
hw_ctrl = cec_read(cec, TEGRA_CEC_HW_CONTROL);
status = cec_read(cec, TEGRA_CEC_INT_STAT);
if ((cec_read(sd, 0x11) & 0x01) == 0) {
nack_cnt = cec_read(sd, 0x14) & 0xf;
low_drive_cnt = cec_read(sd, 0x14) >> 4;
msg.len = cec_read(sd, 0x25) & 0x1f;
msg.msg[i] = cec_read(sd, i + 0x15);
return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
if ((cec_read(sd, 0x11) & 0x01) == 0) {
nack_cnt = cec_read(sd, 0x14) & 0xf;
low_drive_cnt = cec_read(sd, 0x14) >> 4;
msg.len = cec_read(sd, 0x25) & 0x1f;
msg.msg[i] = cec_read(sd, i + 0x15);
return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
reg->val = cec_read(sd, reg->reg & 0xff);