drivers/gpu/drm/gma500/cdv_intel_display.c

235

cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

265

ret = cdv_sb_write(dev, ref_sfr, ref_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

274

ret = cdv_sb_write(dev, SB_M(pipe), m);

drivers/gpu/drm/gma500/cdv_intel_display.c

305

ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);

drivers/gpu/drm/gma500/cdv_intel_display.c

331

ret = cdv_sb_write(dev, SB_P(pipe), p);

drivers/gpu/drm/gma500/cdv_intel_display.c

341

cdv_sb_write(dev, lane_reg, lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

347

cdv_sb_write(dev, lane_reg, lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

353

cdv_sb_write(dev, lane_reg, lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

359

cdv_sb_write(dev, lane_reg, lane_value);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1424

cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1427

cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1434

cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1436

cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1440

cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1442

cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1448

cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1453

cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1457

cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);

drivers/gpu/drm/gma500/psb_intel_drv.h

234

extern int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val);