drivers/gpu/drm/gma500/cdv_intel_display.c

165

if (cdv_sb_read(dev, reg, &temp) == 0)

drivers/gpu/drm/gma500/cdv_intel_display.c

190

if (cdv_sb_read(dev, reg, &temp) == 0)

drivers/gpu/drm/gma500/cdv_intel_display.c

252

ret = cdv_sb_read(dev, ref_sfr, &ref_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

269

ret = cdv_sb_read(dev, SB_M(pipe), &m);

drivers/gpu/drm/gma500/cdv_intel_display.c

278

ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);

drivers/gpu/drm/gma500/cdv_intel_display.c

309

ret = cdv_sb_read(dev, SB_P(pipe), &p);

drivers/gpu/drm/gma500/cdv_intel_display.c

338

cdv_sb_read(dev, lane_reg, &lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

344

cdv_sb_read(dev, lane_reg, &lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

350

cdv_sb_read(dev, lane_reg, &lane_value);

drivers/gpu/drm/gma500/cdv_intel_display.c

356

cdv_sb_read(dev, lane_reg, &lane_value);

drivers/gpu/drm/gma500/psb_intel_drv.h

233

extern int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val);