ccfifo_writel
ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0);
ccfifo_writel(emc, mr13_flip_fspwr ^ 0x40, EMC_MRW3, 0);
ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &
ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &
ccfifo_writel(emc,
ccfifo_writel(emc,
ccfifo_writel(emc,
ccfifo_writel(emc,
ccfifo_writel(emc,
ccfifo_writel(emc, mr13_flip_fspop | 0x8, EMC_MRW3, value);
ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);
ccfifo_writel(emc, emc_pin & ~(EMC_PIN_PIN_CKE_PER_DEV |
ccfifo_writel(emc, 0x0, EMC_CFG_SYNC, delay);
ccfifo_writel(emc, value, EMC_DBG, 0);
ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE, 0);
ccfifo_writel(emc, value, EMC_DBG, 0);
ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
ccfifo_writel(emc, value, EMC_PIN, 0);
ccfifo_writel(emc,
ccfifo_writel(emc, value, EMC_MRW3, delay);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
ccfifo_writel(emc,
ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
ccfifo_writel(emc, value, EMC_MRW3, 0);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_CAL_CMD,
ccfifo_writel(emc, value, EMC_MRW3, delay);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,
ccfifo_writel(emc, 0, 0, 10);
ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);
ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0);
ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);
ccfifo_writel(emc, next->emc_emrs &
ccfifo_writel(emc, next->emc_emrs2 &
ccfifo_writel(emc, next->emc_mrs |
ccfifo_writel(emc, value, EMC_MRS_WAIT_CNT2, 0);
ccfifo_writel(emc, 2 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |
ccfifo_writel(emc, value, EMC_MRW, 0);
ccfifo_writel(emc, value |
ccfifo_writel(emc, value, EMC_ZQ_CAL, 0);
ccfifo_writel(emc,
ccfifo_writel(emc, 0, EMC_REF, 0);
ccfifo_writel(emc, 1, EMC_ISSUE_QRST, 0);
ccfifo_writel(emc, 0, EMC_ISSUE_QRST, 2);
ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &
ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
ccfifo_writel(emc, emc_cfg_pipe_clk, EMC_CFG_PIPE_CLK, 0);
ccfifo_writel(emc, 1, EMC_SELF_REF, 0);
ccfifo_writel(emc, common_tx & 0xa,
ccfifo_writel(emc, common_tx & 0xf,
ccfifo_writel(emc, common_tx | 0x8,
ccfifo_writel(emc, cmd_pad,
ccfifo_writel(emc, dq_pad,
ccfifo_writel(emc, rfu1 & 0xfe40fe40,
ccfifo_writel(emc, rfu1 & 0xfe40fe40,
ccfifo_writel(emc, rfu1 & 0xfeedfeed,
ccfifo_writel(emc, cmd_pad,
ccfifo_writel(emc, dq_pad,
ccfifo_writel(emc, rfu1,
ccfifo_writel(emc, rfu1,
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
ccfifo_writel(emc, rfu1 | 0x06000600,
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
ccfifo_writel(emc, rfu1 | 0x00000600,
ccfifo_writel(emc, cfg5 & ~EMC_FBIO_CFG5_CMD_TX_DIS,
ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 5);
ccfifo_writel(emc, cmd_pad, EMC_PMACRO_CMD_PAD_TX_CTRL, 0);
ccfifo_writel(emc, cfg5 | EMC_FBIO_CFG5_CMD_TX_DIS,
ccfifo_writel(emc, cmd_pad,
ccfifo_writel(emc, dq_pad,
ccfifo_writel(emc, rfu1 & ~0x01120112,
ccfifo_writel(emc, rfu1 & ~0x01120112,
ccfifo_writel(emc, rfu1 & ~0x01bf01bf,
ccfifo_writel(emc, cmd_pad,
ccfifo_writel(emc, dq_pad,
ccfifo_writel(emc, rfu1 & ~0x07ff07ff,
ccfifo_writel(emc, rfu1 & ~0x07ff07ff,
ccfifo_writel(emc, rfu1 & ~0xffff07ff,
ccfifo_writel(emc, common_tx & ~0x5,
ccfifo_writel(emc, common_tx & ~0xf,
ccfifo_writel(emc, 0, 0, seq_wait);
ccfifo_writel(emc, common_tx & ~0xf,