drivers/char/hw_random/cctrng.c

298

tmp_smpl_cnt = cc_ioread(drvdata, CC_SAMPLE_CNT1_REG_OFFSET);

drivers/char/hw_random/cctrng.c

329

isr = cc_ioread(drvdata, CC_RNG_ISR_REG_OFFSET);

drivers/char/hw_random/cctrng.c

359

buf[drvdata->circ.head] = cc_ioread(drvdata,

drivers/char/hw_random/cctrng.c

412

irr = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);

drivers/char/hw_random/cctrng.c

516

val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);

drivers/char/hw_random/cctrng.c

522

cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &

drivers/char/hw_random/cctrng.c

596

val = cc_ioread(drvdata, CC_NVM_IS_IDLE_REG_OFFSET);

drivers/char/hw_random/cctrng.c

630

cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &

drivers/crypto/ccree/cc_driver.c

109

cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));

drivers/crypto/ccree/cc_driver.c

135

ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST));

drivers/crypto/ccree/cc_driver.c

163

idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]);

drivers/crypto/ccree/cc_driver.c

194

irr = cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_driver.c

200

imr = cc_ioread(drvdata, CC_REG(HOST_IMR));

drivers/crypto/ccree/cc_driver.c

231

axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));

drivers/crypto/ccree/cc_driver.c

260

val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));

drivers/crypto/ccree/cc_driver.c

280

val = cc_ioread(drvdata, CC_REG(AXIM_CFG));

drivers/crypto/ccree/cc_driver.c

283

cc_ioread(drvdata, CC_REG(AXIM_CFG)));

drivers/crypto/ccree/cc_driver.c

287

val = cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_driver.c

406

val = cc_ioread(new_drvdata, new_drvdata->sig_offset);

drivers/crypto/ccree/cc_driver.c

414

hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);

drivers/crypto/ccree/cc_driver.c

436

val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));

drivers/crypto/ccree/cc_driver.c

454

val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));

drivers/crypto/ccree/cc_fips.c

26

reg = cc_ioread(drvdata, CC_REG(GPR_HOST));

drivers/crypto/ccree/cc_request_mgr.c

145

req_mgr_h->hw_queue_size = cc_ioread(drvdata,

drivers/crypto/ccree/cc_request_mgr.c

248

cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));

drivers/crypto/ccree/cc_request_mgr.c

526

cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));

drivers/crypto/ccree/cc_request_mgr.c

609

cc_ioread(drvdata, drvdata->axim_mon_offset));

drivers/crypto/ccree/cc_request_mgr.c

638

drvdata->irq |= cc_ioread(drvdata, CC_REG(HOST_IRR));

drivers/crypto/ccree/cc_request_mgr.c

658

cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~drvdata->comp_mask);

drivers/crypto/ccree/cc_sram_mgr.c

24

start = cc_ioread(drvdata, CC_REG(HOST_SEP_SRAM_THRESHOLD));