drivers/gpu/drm/bridge/sii9234.c

331

cbus_writeb(ctx, 0xE0 + i, 0xF2);

drivers/gpu/drm/bridge/sii9234.c

336

cbus_writeb(ctx, 0xF0 + i, 0xF2);

drivers/gpu/drm/bridge/sii9234.c

345

cbus_writeb(ctx, 0x07, 0xF2);

drivers/gpu/drm/bridge/sii9234.c

346

cbus_writeb(ctx, 0x40, 0x03);

drivers/gpu/drm/bridge/sii9234.c

347

cbus_writeb(ctx, 0x42, 0x06);

drivers/gpu/drm/bridge/sii9234.c

348

cbus_writeb(ctx, 0x36, 0x0C);

drivers/gpu/drm/bridge/sii9234.c

349

cbus_writeb(ctx, 0x3D, 0xFD);

drivers/gpu/drm/bridge/sii9234.c

350

cbus_writeb(ctx, 0x1C, 0x01);

drivers/gpu/drm/bridge/sii9234.c

351

cbus_writeb(ctx, 0x1D, 0x0F);

drivers/gpu/drm/bridge/sii9234.c

352

cbus_writeb(ctx, 0x44, 0x02);

drivers/gpu/drm/bridge/sii9234.c

354

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);

drivers/gpu/drm/bridge/sii9234.c

355

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,

drivers/gpu/drm/bridge/sii9234.c

357

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,

drivers/gpu/drm/bridge/sii9234.c

359

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);

drivers/gpu/drm/bridge/sii9234.c

360

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);

drivers/gpu/drm/bridge/sii9234.c

361

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,

drivers/gpu/drm/bridge/sii9234.c

363

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,

drivers/gpu/drm/bridge/sii9234.c

365

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,

drivers/gpu/drm/bridge/sii9234.c

367

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);

drivers/gpu/drm/bridge/sii9234.c

368

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,

drivers/gpu/drm/bridge/sii9234.c

371

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);

drivers/gpu/drm/bridge/sii9234.c

372

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);

drivers/gpu/drm/bridge/sii9234.c

373

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,

drivers/gpu/drm/bridge/sii9234.c

375

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,

drivers/gpu/drm/bridge/sii9234.c

377

cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);

drivers/gpu/drm/bridge/sii9234.c

379

cbus_writeb(ctx, 0x30, 0x01);

drivers/gpu/drm/bridge/sii9234.c

383

cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0);

drivers/gpu/drm/bridge/sii9234.c

384

cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0);

drivers/gpu/drm/bridge/sii9234.c

675

cbus_writeb(ctx, 0x07, 0x32);

drivers/gpu/drm/bridge/sii9234.c

792

cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF);

drivers/gpu/drm/bridge/sii9234.c

793

cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF);

drivers/gpu/drm/bridge/sii9234.c

794

cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1);

drivers/gpu/drm/bridge/sii9234.c

795

cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);