carl9170_write_reg
int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val);
err = carl9170_write_reg(ar, reg, val);
struct carl9170_write_reg wreg;
return carl9170_write_reg(ar, AR9170_GPIO_REG_PORT_DATA, led_state);
err = carl9170_write_reg(ar, AR9170_GPIO_REG_PORT_TYPE, 3);
return carl9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME,
return carl9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
return carl9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
return carl9170_write_reg(ar, AR9170_MAC_REG_RTS_CTS_RATE,
err = carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER,
carl9170_write_reg(ar, AR9170_MAC_REG_DMA_TRIGGER, 0);
err = carl9170_write_reg(ar, ar->fw.tx_seq_table + vif_id * 4,
err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET,
err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, 0x0);
err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
err = carl9170_write_reg(ar, AR9170_PHY_REG_TURBO, tmp);
err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC,