carl9170_regwrite
carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, basic);
carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, mandatory);
carl9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
carl9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
carl9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
carl9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
carl9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
carl9170_regwrite(AR9170_MAC_REG_AC2_AC1_AC0_AIFS,
carl9170_regwrite(AR9170_MAC_REG_AC4_AC3_AC2_AIFS,
carl9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
carl9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
carl9170_regwrite(0x1c3600, 0x3);
carl9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
carl9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0x0);
carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
carl9170_regwrite(AR9170_MAC_REG_SNIFFER,
carl9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
carl9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
carl9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
carl9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
carl9170_regwrite(AR9170_MAC_REG_TID_CFACK_CFEND_RATE, 0x59900000);
carl9170_regwrite(AR9170_MAC_REG_TXOP_DURATION, 0x201);
carl9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
carl9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0x8000a);
carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a07);
carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL,
carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x0030033);
carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, 0x4003c1e);
carl9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
carl9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
carl9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
carl9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
carl9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
carl9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, 0xffffffff);
carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, 0xffffffff);
carl9170_regwrite(AR9170_MAC_REG_PRETBTT, 0x0);
carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, 0x0);
carl9170_regwrite(reg, get_unaligned_le32(mac));
carl9170_regwrite(reg + 4, get_unaligned_le16(mac + 4));
carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32);
carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash);
carl9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
carl9170_regwrite(AR9170_MAC_REG_CAM_MODE, cam_mode);
carl9170_regwrite(AR9170_MAC_REG_ENCRYPTION, enc_mode);
carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL, rx_ctrl);
carl9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
carl9170_regwrite(AR9170_MAC_REG_ACK_TPC,
carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC,
carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC,
carl9170_regwrite(0x1c58b0, fd0);
carl9170_regwrite(0x1c58e8, fd1);
carl9170_regwrite(0x1c6280 + chain * 0x1000 +
carl9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
carl9170_regwrite(AR9170_PHY_REG_SWITCH_COM,
carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_0,
carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_2,
carl9170_regwrite(AR9170_PHY_REG_SETTLING, val);
carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val);
carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f);
carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val);
carl9170_regwrite(0x1c8864, val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val);
carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val);
carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val);
carl9170_regwrite(AR9170_PHY_REG_RX_CHAINMASK, ar->eeprom.rx_mask);
carl9170_regwrite(AR9170_PHY_REG_CAL_CHAINMASK, ar->eeprom.rx_mask);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f);
carl9170_regwrite(ar5416_phy_init[i].reg, val);
carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f);
carl9170_regwrite(carl9170_rf_initval[i].reg,