drivers/gpu/drm/amd/amdkfd/kfd_crat.c

1197

props->cacheline_size = cache->cache_line_size;

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1643

pcache->cacheline_size = pcache_info[cache_type].cache_line_size;

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

1727

pcache->cacheline_size = pcache_info[cache_type].cache_line_size;

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

342

cache->cacheline_size);

drivers/gpu/drm/amd/amdkfd/kfd_topology.h

105

uint32_t cacheline_size;

drivers/gpu/drm/i915/display/i9xx_wm.c

2170

i965_cursor_wm_info.cacheline_size) +

drivers/gpu/drm/i915/display/i9xx_wm.c

2335

entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);

drivers/gpu/drm/i915/display/i9xx_wm.c

32

u8 cacheline_size;

drivers/gpu/drm/i915/display/i9xx_wm.c

377

.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

385

.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

393

.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

401

.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

409

.cacheline_size = I915_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

417

.cacheline_size = I915_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

425

.cacheline_size = I915_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

433

.cacheline_size = I830_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

441

.cacheline_size = I830_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

449

.cacheline_size = I830_FIFO_LINE_SIZE,

drivers/gpu/drm/i915/display/i9xx_wm.c

584

entries = DIV_ROUND_UP(entries, wm->cacheline_size) +

drivers/net/ethernet/broadcom/tg3.c

17124

int cacheline_size;

drivers/net/ethernet/broadcom/tg3.c

17130

cacheline_size = 1024;

drivers/net/ethernet/broadcom/tg3.c

17132

cacheline_size = (int) byte * 4;

drivers/net/ethernet/broadcom/tg3.c

17172

switch (cacheline_size) {

drivers/net/ethernet/broadcom/tg3.c

17197

switch (cacheline_size) {

drivers/net/ethernet/broadcom/tg3.c

17214

switch (cacheline_size) {

drivers/pci/pci.c

4172

u8 cacheline_size;

drivers/pci/pci.c

4179

pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);

drivers/pci/pci.c

4180

if (cacheline_size >= pci_cache_line_size &&

drivers/pci/pci.c

4181

(cacheline_size % pci_cache_line_size) == 0)

drivers/pci/pci.c

4187

pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);

drivers/pci/pci.c

4188

if (cacheline_size == pci_cache_line_size)

drivers/scsi/myrb.h

297

unsigned short cacheline_size; /* Bytes 104-105 */

drivers/scsi/myrs.c

1575

if (ldev_info->cacheline_size) {

drivers/scsi/myrs.c

1577

put_unaligned_be16(1 << ldev_info->cacheline_size,

drivers/scsi/myrs.h

413

enum myrs_cacheline_size cacheline_size; /* Byte 7 */

tools/perf/util/cacheline.h

16

u64 size = cacheline_size();

tools/perf/util/cacheline.h

27

u64 size = cacheline_size();

tools/perf/util/cacheline.h

7

int __pure cacheline_size(void);

tools/perf/util/sort.c

2486

int cln_size = cacheline_size();

tools/perf/util/sort.c

2514

int cln_size = cacheline_size();

tools/perf/util/sort.c

3586

} else if (sd->entry == &sort_mem_dcacheline && cacheline_size() == 0) {

tools/perf/util/sort.c

3834

if (!cacheline_size() && !strncasecmp(tok, "dcacheline", strlen(tok)))