arch/arc/kernel/perf_event.c

303

unsigned int cache_type, cache_op, cache_result;

arch/arc/kernel/perf_event.c

307

cache_op = (config >> 8) & 0xff;

arch/arc/kernel/perf_event.c

311

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/arc/kernel/perf_event.c

316

ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];

arch/arc/kernel/perf_event.c

322

cache_type, cache_op, cache_result, ret,

arch/csky/kernel/perf_event.c

952

unsigned int cache_type, cache_op, cache_result;

arch/csky/kernel/perf_event.c

955

cache_op = (config >> 8) & 0xff;

arch/csky/kernel/perf_event.c

960

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/csky/kernel/perf_event.c

965

return csky_pmu_cache_map[cache_type][cache_op][cache_result];

arch/csky/mm/dma-mapping.c

55

cache_op(page_to_phys(page), size, dma_wbinv_set_zero_range);

arch/csky/mm/dma-mapping.c

63

cache_op(paddr, size, dma_wb_range);

arch/csky/mm/dma-mapping.c

67

cache_op(paddr, size, dma_wbinv_range);

arch/csky/mm/dma-mapping.c

82

cache_op(paddr, size, dma_inv_range);

arch/loongarch/include/asm/cacheflush.h

61

cache_op(Index_Writeback_Inv_LEAF0, addr);

arch/loongarch/include/asm/cacheflush.h

64

cache_op(Index_Writeback_Inv_LEAF1, addr);

arch/loongarch/include/asm/cacheflush.h

67

cache_op(Index_Writeback_Inv_LEAF2, addr);

arch/loongarch/include/asm/cacheflush.h

70

cache_op(Index_Writeback_Inv_LEAF3, addr);

arch/loongarch/include/asm/cacheflush.h

73

cache_op(Index_Writeback_Inv_LEAF4, addr);

arch/loongarch/include/asm/cacheflush.h

76

cache_op(Index_Writeback_Inv_LEAF5, addr);

arch/loongarch/kernel/perf_event.c

603

unsigned int cache_type, cache_op, cache_result;

arch/loongarch/kernel/perf_event.c

610

cache_op = (config >> 8) & 0xff;

arch/loongarch/kernel/perf_event.c

611

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/loongarch/kernel/perf_event.c

620

[cache_op]

arch/mips/include/asm/bmips.h

120

cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);

arch/mips/include/asm/bmips.h

99

cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);

arch/mips/include/asm/r4kcache.h

100

cache_op(Hit_Invalidate_SD, addr);

arch/mips/include/asm/r4kcache.h

105

cache_op(Hit_Writeback_Inv_SD, addr);

arch/mips/include/asm/r4kcache.h

192

cache_op(Page_Invalidate_T, addr);

arch/mips/include/asm/r4kcache.h

297

prot##cache_op(hitop, addr); \

arch/mips/include/asm/r4kcache.h

62

cache_op(Index_Invalidate_I, addr);

arch/mips/include/asm/r4kcache.h

67

cache_op(Index_Writeback_Inv_D, addr);

arch/mips/include/asm/r4kcache.h

72

cache_op(Index_Writeback_Inv_SD, addr);

arch/mips/include/asm/r4kcache.h

79

cache_op(Hit_Invalidate_I_Loongson2, addr);

arch/mips/include/asm/r4kcache.h

83

cache_op(Hit_Invalidate_I, addr);

arch/mips/include/asm/r4kcache.h

90

cache_op(Hit_Writeback_Inv_D, addr);

arch/mips/include/asm/r4kcache.h

95

cache_op(Hit_Invalidate_D, addr);

arch/mips/kernel/mips-mt.c

131

cache_op(Index_Load_Tag_D, INDEX_8);

arch/mips/kernel/mips-mt.c

141

cache_op(Index_Store_Tag_D, INDEX_8);

arch/mips/kernel/mips-mt.c

146

cache_op(Index_Store_Tag_D, INDEX_0);

arch/mips/kernel/perf_event_mipsxx.c

733

unsigned int cache_type, cache_op, cache_result;

arch/mips/kernel/perf_event_mipsxx.c

740

cache_op = (config >> 8) & 0xff;

arch/mips/kernel/perf_event_mipsxx.c

741

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/mips/kernel/perf_event_mipsxx.c

750

[cache_op]

arch/mips/kernel/spram.c

100

cache_op(Index_Load_Tag_D, CKSEG0 | offset);

arch/mips/kernel/spram.c

51

cache_op(Index_Store_Tag_I, CKSEG0|offset);

arch/mips/kernel/spram.c

67

cache_op(Index_Load_Tag_I, CKSEG0 | offset);

arch/mips/kernel/spram.c

86

cache_op(Index_Store_Tag_D, CKSEG0 | offset);

arch/mips/kvm/vz.c

1235

case cache_op:

arch/mips/mm/c-r4k.c

1417

cache_op(Index_Store_Tag_I, begin);

arch/mips/mm/c-r4k.c

1418

cache_op(Index_Store_Tag_D, begin);

arch/mips/mm/c-r4k.c

1419

cache_op(Index_Store_Tag_SD, begin);

arch/mips/mm/c-r4k.c

1424

cache_op(Index_Load_Tag_SD, addr);

arch/mips/mm/sc-mips.c

40

cache_op(Hit_Writeback_Inv_SD, addr & almask);

arch/mips/mm/sc-mips.c

41

cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);

arch/mips/mm/sc-r5k.c

30

cache_op(R5K_Page_Invalidate_S, start);

arch/mips/mm/sc-r5k.c

54

cache_op(R5K_Page_Invalidate_S, a);

arch/mips/mm/sc-rm7k.c

117

cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));

arch/mips/mm/sc-rm7k.c

143

cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));

arch/mips/mm/sc-rm7k.c

210

cache_op(Index_Store_Tag_T, begin);

arch/mips/mm/sc-rm7k.c

215

cache_op(Index_Load_Tag_T, addr);

arch/mips/mm/sc-rm7k.c

99

cache_op(Page_Invalidate_T, start);

arch/mips/mm/uasm-mips.c

68

[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/sgi-ip22/ip28-berr.c

108

cache_op(Index_Load_Tag_I, addr);

arch/mips/sgi-ip22/ip28-berr.c

111

cache_op(Index_Load_Tag_I, addr | 1L);

arch/mips/sgi-ip22/ip28-berr.c

74

cache_op(Index_Load_Tag_S, addr);

arch/mips/sgi-ip22/ip28-berr.c

77

cache_op(Index_Load_Tag_S, addr | 1L);

arch/mips/sgi-ip22/ip28-berr.c

92

cache_op(Index_Load_Tag_D, addr);

arch/mips/sgi-ip22/ip28-berr.c

95

cache_op(Index_Load_Tag_D, addr | 1L);

arch/mips/txx9/generic/setup.c

156

cache_op(Index_Writeback_Inv_D, addr | 0);

arch/mips/txx9/generic/setup.c

157

cache_op(Index_Writeback_Inv_D, addr | 1);

arch/mips/txx9/generic/setup.c

158

cache_op(Index_Writeback_Inv_D, addr | 2);

arch/mips/txx9/generic/setup.c

159

cache_op(Index_Writeback_Inv_D, addr | 3);

arch/riscv/kvm/vcpu_pmu.c

103

cache_op = (sbi_event_code & SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK) >>

arch/riscv/kvm/vcpu_pmu.c

108

cache_op >= PERF_COUNT_HW_CACHE_OP_MAX ||

arch/riscv/kvm/vcpu_pmu.c

112

config = cache_type | (cache_op << 8) | (cache_result << 16);

arch/riscv/kvm/vcpu_pmu.c

98

unsigned int cache_type, cache_op, cache_result;

arch/sparc/kernel/perf_event.c

1198

unsigned int cache_type, cache_op, cache_result;

arch/sparc/kernel/perf_event.c

1208

cache_op = (config >> 8) & 0xff;

arch/sparc/kernel/perf_event.c

1209

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/sparc/kernel/perf_event.c

1216

pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);

arch/x86/events/core.c

381

unsigned int cache_type, cache_op, cache_result;

arch/x86/events/core.c

391

cache_op = (config >> 8) & 0xff;

arch/x86/events/core.c

392

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

arch/x86/events/core.c

394

cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);

arch/x86/events/core.c

401

val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];

arch/x86/events/core.c

409

attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];

arch/xtensa/kernel/perf_event.c

115

unsigned int cache_type, cache_op, cache_result;

arch/xtensa/kernel/perf_event.c

119

cache_op = (config >> 8) & 0xff;

arch/xtensa/kernel/perf_event.c

123

cache_op >= C(OP_MAX) ||

arch/xtensa/kernel/perf_event.c

127

ret = xtensa_cache_ctl[cache_type][cache_op][cache_result];

drivers/perf/arm_pmu.c

131

unsigned int cache_type, cache_op, cache_result, ret;

drivers/perf/arm_pmu.c

137

cache_op = (config >> 8) & 0xff;

drivers/perf/arm_pmu.c

138

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

drivers/perf/arm_pmu.c

148

ret = (int)(*cache_map)[cache_type][cache_op][cache_result];

drivers/perf/riscv_pmu_sbi.c

612

unsigned int cache_type, cache_op, cache_result, ret;

drivers/perf/riscv_pmu_sbi.c

618

cache_op = (config >> 8) & 0xff;

drivers/perf/riscv_pmu_sbi.c

619

if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)

drivers/perf/riscv_pmu_sbi.c

626

ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx;

tools/perf/util/parse-events.c

1022

int cache_type, cache_op, cache_result;

tools/perf/util/parse-events.c

1027

cache_op = (term->val.num >> 8) & 0xFF;

tools/perf/util/parse-events.c

1031

cache_op >= PERF_COUNT_HW_CACHE_OP_MAX ||

tools/perf/util/parse-events.c

367

int len, cache_type = -1, cache_op = -1, cache_result = -1;

tools/perf/util/parse-events.c

377

cache_op = parse_aliases(str, evsel__hw_cache_op,

tools/perf/util/parse-events.c

379

if (cache_op >= 0) {

tools/perf/util/parse-events.c

380

if (!evsel__is_cache_op_valid(cache_type, cache_op))

tools/perf/util/parse-events.c

391

if (cache_op < 0) {

tools/perf/util/parse-events.c

392

cache_op = parse_aliases(str, evsel__hw_cache_op,

tools/perf/util/parse-events.c

394

if (cache_op >= 0) {

tools/perf/util/parse-events.c

395

if (!evsel__is_cache_op_valid(cache_type, cache_op))

tools/perf/util/parse-events.c

407

if (cache_op == -1)

tools/perf/util/parse-events.c

408

cache_op = PERF_COUNT_HW_CACHE_OP_READ;

tools/perf/util/parse-events.c

416

*config = cache_type | (cache_op << 8) | (cache_result << 16);

tools/perf/util/pmu.c

1552

int cache_op = (term->val.num >> 8) & 0xFF;

tools/perf/util/pmu.c

1556

assert(cache_op < PERF_COUNT_HW_CACHE_OP_MAX);