bnx2_write_phy
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
bnx2_write_phy(bp, bp->mii_up1, up1);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
bnx2_write_phy(bp, bp->mii_up1, up1);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
bnx2_write_phy(bp, bp->mii_adv, adv &
bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
bnx2_write_phy(bp, bp->mii_adv, adv);
bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
bnx2_write_phy(bp, bp->mii_adv, new_adv);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
bnx2_write_phy(bp, bp->mii_adv, new_adv);
bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
bnx2_write_phy(bp, bp->mii_adv, new_adv);
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
bnx2_write_phy(bp, BCM5708S_UP1, val);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
bnx2_write_phy(bp, 0x18, 0x7);
bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
bnx2_write_phy(bp, 0x1c, 0x6c00);
bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
bnx2_write_phy(bp, 0x18, 0x7);
bnx2_write_phy(bp, 0x18, val & ~0x4007);
bnx2_write_phy(bp, 0x1c, 0x6c00);
bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
bnx2_write_phy(bp, 0x18, 0x0c00);
bnx2_write_phy(bp, 0x17, 0x000a);
bnx2_write_phy(bp, 0x15, 0x310b);
bnx2_write_phy(bp, 0x17, 0x201f);
bnx2_write_phy(bp, 0x15, 0x9506);
bnx2_write_phy(bp, 0x17, 0x401f);
bnx2_write_phy(bp, 0x15, 0x14e2);
bnx2_write_phy(bp, 0x18, 0x0400);
bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
bnx2_write_phy(bp, 0x18, 0x7);
bnx2_write_phy(bp, 0x18, val | 0x4000);
bnx2_write_phy(bp, 0x10, val | 0x1);
bnx2_write_phy(bp, 0x18, 0x7);
bnx2_write_phy(bp, 0x18, val & ~0x4007);
bnx2_write_phy(bp, 0x10, val & ~0x1);
bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);
bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);
rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
bnx2_write_phy(bp, 0x17, 0x0f01);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);