bmwrite
bmwrite(dev, SROMCSR, ChipSelect | Clk);
bmwrite(dev, SROMCSR, ChipSelect);
bmwrite(dev, SROMCSR, data | ChipSelect );
bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
bmwrite(dev, SROMCSR, data | ChipSelect);
bmwrite(dev, SROMCSR, 0);
bmwrite(dev, SROMCSR, 0);
bmwrite(dev, INTDISABLE, EnableNormal);
bmwrite(dev, INTDISABLE, DisableAll);
bmwrite(dev, INTDISABLE, DisableAll);
bmwrite(dev, RXCFG, (config & ~RxMACEnable));
bmwrite(dev, TXCFG, (config & ~TxMACEnable));
bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
bmwrite(dev, RXCFG, (config & ~RxMACEnable));
bmwrite(dev, TXCFG, (config & ~TxMACEnable));
bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
bmwrite(dev, MIFCSR, 0);
bmwrite(dev, MIFCSR, 1);
bmwrite(dev, MIFCSR, 0);
bmwrite(dev, MIFCSR, 1);
bmwrite(dev, MIFCSR, b);
bmwrite(dev, MIFCSR, b|1);
bmwrite(dev, MIFCSR, 4);
bmwrite(dev, MIFCSR, 2);
bmwrite(dev, MIFCSR, 1);
bmwrite(dev, MIFCSR, 4);
bmwrite(dev, MIFCSR, 4);
bmwrite(dev, RXRST, RxResetValue);
bmwrite(dev, TXRST, TxResetBit);
bmwrite(dev, XCVRIF, regValue);
bmwrite(dev, RSEED, (unsigned short)0x1968);
bmwrite(dev, XIFC, regValue);
bmwrite(dev, NCCNT, 0);
bmwrite(dev, NTCNT, 0);
bmwrite(dev, EXCNT, 0);
bmwrite(dev, LTCNT, 0);
bmwrite(dev, FRCNT, 0);
bmwrite(dev, LECNT, 0);
bmwrite(dev, AECNT, 0);
bmwrite(dev, FECNT, 0);
bmwrite(dev, RXCV, 0);
bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
bmwrite(dev, MADD0, *pWord16++);
bmwrite(dev, MADD1, *pWord16++);
bmwrite(dev, MADD2, *pWord16);
bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
bmwrite(dev, INTDISABLE, EnableNormal);
bmwrite(dev, INTDISABLE, DisableAll);
bmwrite(dev, INTDISABLE, EnableNormal);
bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
bmwrite(dev, RXCFG, (config & ~RxMACEnable));
bmwrite(dev, TXCFG, (config & ~TxMACEnable));
bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
bmwrite(dev, MADD0, *pWord16++);
bmwrite(dev, MADD1, *pWord16++);
bmwrite(dev, MADD2, *pWord16);
bmwrite(dev, RXCFG, rx_cfg);
bmwrite(dev, RXRST, RxResetValue);
bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
bmwrite(dev, RXCFG, rx_cfg );
bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
bmwrite(dev, RXCFG, rx_cfg);
bmwrite(dev, BHASH0, 0xffff);
bmwrite(dev, BHASH1, 0xffff);
bmwrite(dev, BHASH2, 0xffff);
bmwrite(dev, BHASH3, 0xffff);
bmwrite(dev, RXCFG, rx_cfg);
bmwrite(dev, RXCFG, rx_cfg);
bmwrite(dev, BHASH0, hash_table[0]);
bmwrite(dev, BHASH1, hash_table[1]);
bmwrite(dev, BHASH2, hash_table[2]);
bmwrite(dev, BHASH3, hash_table[3]);