block_sequence
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz;
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
block_sequence[num_steps].params.update_pstate_support_params.support = false;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
block_sequence[num_steps].params.update_hardmin_params.freq_mhz =
block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;
block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
block_sequence[num_steps].params.update_dentist_params.context = context;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
block_sequence[num_steps].params.update_dentist_params.context = context;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;
block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;
params = &clk_mgr401->block_sequence[i].params;
switch (clk_mgr401->block_sequence[i].func) {
struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
block_sequence[num_steps].params.update_pstate_support_params.support = true;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz;
struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE];
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
struct block_sequence_state seq_state = { .steps = block_sequence, .num_steps = num_steps };
update_type, context, context->block_sequence, &num_steps);
hwss_execute_sequence(dc, context->block_sequence, num_steps);
context->block_sequence,
context->block_sequence,
block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
block_sequence[*num_steps].params.cursor_lock_params.lock = false;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.opp_program_fmt_params.opp = current_pipe->stream_res.opp;
block_sequence[*num_steps].params.opp_program_fmt_params.fmt_bit_depth = ¤t_pipe->stream->bit_depth_params;
block_sequence[*num_steps].params.opp_program_fmt_params.clamping = ¤t_pipe->stream->clamping;
block_sequence[*num_steps].func = OPP_PROGRAM_FMT;
block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;
block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = DPP_SETUP_DPP;
block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
block_sequence[*num_steps].params.control_cm_hist_params.dpp
block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control
block_sequence[*num_steps].params.control_cm_hist_params.color_space
block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp;
block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space;
block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = ¤t_mpc_pipe->plane_state->cursor_csc_color_matrix;
block_sequence[*num_steps].func = DPP_SET_CURSOR_MATRIX;
block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;
block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;
block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW;
block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
params = &(block_sequence[i].params);
switch (block_sequence[i].func) {
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;
block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;
block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;
block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc;
block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx;
block_sequence[*num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT;
block_sequence[*num_steps].params.update_info_frame_params.dc = dc;
block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx;
block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME;
block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link;
block_sequence[*num_steps].params.dp_trace_source_sequence_params.source = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME;
block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE;
block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp;
block_sequence[*num_steps].params.set_dmdata_attributes_params.attr = attr;
block_sequence[*num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES;
block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
block_sequence[*num_steps].params.cursor_lock_params.lock = true;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =
block_sequence[*num_steps].params.cursor_lock_params.lock = true;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp =
block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.attributes =
block_sequence[*num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES;
block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp =
block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.attributes =
block_sequence[*num_steps].func = DPP_SET_CURSOR_ATTRIBUTES;
block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =
block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx =
block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU;
block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc;
block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx =
block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;
block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
block_sequence[*num_steps].params.cursor_lock_params.lock = false;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =
block_sequence[*num_steps].params.cursor_lock_params.lock = false;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
block_sequence[*num_steps].params.cursor_lock_params.lock = true;
block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
block_sequence[*num_steps].params.set_cursor_position_params.dc = dc;
block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe;
block_sequence[*num_steps].func = SET_CURSOR_POSITION;
block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =
block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx =
block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU;
memset(state->block_sequence, 0, sizeof(state->block_sequence));
struct block_sequence *steps;
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],
struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE];