bootstrap
u32 bootstrap;
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
u32 bootstrap;
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
# All cores other than the master need to wait here for SMP bootstrap
struct legacy_bootstrap_region bootstrap;
struct xt_table_info *bootstrap,
kmem_cache = bootstrap(&boot_kmem_cache);
kmem_cache_node = bootstrap(&boot_kmem_cache_node);
struct xt_table_info bootstrap = {0};
new_table = xt_register_table(net, table, &bootstrap, newinfo);
struct xt_table_info bootstrap = {0};
new_table = xt_register_table(net, table, &bootstrap, newinfo);
struct xt_table_info bootstrap = {0};
new_table = xt_register_table(net, table, &bootstrap, newinfo);
struct xt_table_info *bootstrap,
table->private = bootstrap;
bool bootstrap = false;
bootstrap = !commands[i].func;
jsonw_bool_field(json_wtr, "bootstrap", bootstrap);
print_feature("bootstrap", bootstrap, &nb_features);
bootstrap(argv[0]);