bnx2_shmem_rd
link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
bnx2_shmem_rd(bp, BNX2_DRV_MB),
bnx2_shmem_rd(bp, BNX2_FW_MB),
bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
val = bnx2_shmem_rd(bp, BNX2_FW_MB);
val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
bnx2_shmem_rd(bp, offset), \
bnx2_shmem_rd(bp, offset + 4), \
bnx2_shmem_rd(bp, offset + 8), \
bnx2_shmem_rd(bp, offset + 12))