drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1000

block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1001

block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1002

block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1009

block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1010

block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1011

block_sequence[num_steps].params.update_hardmin_params.response = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1012

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1020

block_sequence[num_steps].params.update_pstate_support_params.support = false;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1021

block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1053

block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1054

block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1057

block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1058

block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1068

block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1069

block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1087

struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1122

block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1123

block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1124

block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1125

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1129

block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1130

block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1131

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1148

block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1149

block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1150

block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1151

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1160

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1161

block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1162

block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1163

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1166

block_sequence[num_steps].params.update_dentist_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1167

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1171

block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1172

block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1173

block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1174

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1177

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1178

block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1179

block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1180

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1186

block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1187

block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1188

block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1189

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1194

block_sequence[num_steps].params.update_dentist_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1195

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1199

block_sequence[num_steps].params.update_dppclk_dto_params.context = context;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1200

block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1201

block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1202

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1209

block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1210

block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1211

block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

653

params = &clk_mgr401->block_sequence[i].params;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

655

switch (clk_mgr401->block_sequence[i].func) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

773

struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

808

block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

809

block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

848

block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

849

block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

850

block_sequence[num_steps].params.update_hardmin_params.response = NULL;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

851

block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

860

block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

861

block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

877

block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

878

block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

881

block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

882

block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

893

block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

894

block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

909

block_sequence[num_steps].params.update_pstate_support_params.support = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

910

block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

984

block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

985

block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

986

block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

992

block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

993

block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

994

block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

104

struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE];

drivers/gpu/drm/amd/display/dc/core/dc.c

4153

context->block_sequence,

drivers/gpu/drm/amd/display/dc/core/dc.c

4159

context->block_sequence,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

733

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

753

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

754

block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

755

block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

759

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

760

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

761

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

763

block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

770

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

771

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

772

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

773

block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

777

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

778

block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

779

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

780

block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

785

block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

786

block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

787

block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

788

block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

798

block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

799

block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

800

block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

804

block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

805

block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

806

block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

807

block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

813

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

814

block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

815

block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

816

block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

820

block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

821

block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

822

block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

827

block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

828

block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

829

block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

830

block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

835

block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

836

block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

840

block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

841

block_sequence[*num_steps].func = DPP_SETUP_DPP;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

845

block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

846

block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

851

block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

852

block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

853

block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

854

block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

859

block_sequence[*num_steps].params.update_visual_confirm_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

860

block_sequence[*num_steps].params.update_visual_confirm_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

861

block_sequence[*num_steps].params.update_visual_confirm_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

862

block_sequence[*num_steps].func = MPC_UPDATE_VISUAL_CONFIRM;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

866

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

867

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

868

block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

869

block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

873

block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

874

block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

875

block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

876

block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

877

block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

880

block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

881

block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

882

block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

883

block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

884

block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

894

block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

895

block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

896

block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

897

block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

901

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

902

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

903

block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

905

block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

909

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

910

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

911

block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

912

block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

926

block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

927

block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

928

block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

932

block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

933

block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

943

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

951

params = &(block_sequence[i].params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

952

switch (block_sequence[i].func) {

drivers/gpu/drm/amd/display/dc/core/dc_state.c

335

memset(state->block_sequence, 0, sizeof(state->block_sequence));

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1369

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1375

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE],

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

987

struct block_sequence *steps;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

663

struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE];