bgmac_read
bgmac_read(bgmac, BGMAC_INT_MASK);
mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
val |= bgmac_read(bgmac, s->offset);
empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
val = bgmac_read(bgmac, reg);
ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
bgmac_read(bgmac,
bgmac_read(bgmac,
bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
return bgmac_read(bgmac, BGMAC_UNIMAC + offset);
bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set);