b43_write32
b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
b43_write32(dev, addr, val);
b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
b43_write32(dev, mmio_base + offset, 0);
b43_write32(dev, mmio_base + offset, 0);
b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
b43_write32(ring->dev, ring->mmio_base + offset, value);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, B43_MMIO_MACCMD,
b43_write32(dev, B43_MMIO_MACCMD,
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
b43_write32(dev, B43_MMIO_MACCMD, cmd);
b43_write32(dev, B43_MMIO_MACCMD, cmd);
b43_write32(dev, B43_MMIO_MACCMD, cmd);
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
b43_write32(dev, offset, value);
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
b43_write32(dev, B43_MMIO_MACCTL, ctl);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, 0x0100, 0x01000000);
b43_write32(dev, 0x010C, 0x01000000);
b43_write32(dev, 0x0188, 0x80000000);
b43_write32(dev, 0x018C, 0x02000000);
b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
b43_write32(dev, B43_MMIO_RAM_DATA, val);
b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
b43_write32(dev, B43_MMIO_SHM_DATA, value);
b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, B43_MMIO_MACCTL, macctl);
b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
b43_write32(q->dev, q->mmio_base + offset, value);
b43_write32(q->dev, q->mmio_base + offset, value);