b43_read32
b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
val = b43_read32(dev, addr);
val = b43_read32(dev, addr);
ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
value = b43_read32(dev, mmio_base + offset);
value = b43_read32(dev, mmio_base + offset);
value = b43_read32(dev, mmio_base + offset);
tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
return b43_read32(ring->dev, ring->mmio_base + offset);
macctl = b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
macctl = b43_read32(dev, B43_MMIO_MACCTL);
v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
b43_read32(dev, B43_MMIO_MACCMD)
tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
cmd = b43_read32(dev, B43_MMIO_MACCMD);
cmd = b43_read32(dev, B43_MMIO_MACCMD);
cmd = b43_read32(dev, B43_MMIO_MACCMD);
cmd = b43_read32(dev, B43_MMIO_MACCMD);
if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
macctl = b43_read32(dev, B43_MMIO_MACCTL);
tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
b43_read32(dev, B43_MMIO_MACCTL);
tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
ctl = b43_read32(dev, B43_MMIO_MACCTL);
v = b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
macctl = b43_read32(dev, B43_MMIO_MACCTL);
u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP);
ret = b43_read32(dev, B43_MMIO_SHM_DATA);
low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
macctl = b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
macctl = b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
b43_read32(dev, B43_MMIO_MACCTL);
if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
return b43_read32(q->dev, q->mmio_base + offset);
return b43_read32(q->dev, q->mmio_base + offset);
b43_read32(dev, B43_MMIO_MACCTL); /* flush */
return !(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)