axienet_iow
axienet_iow(lp, XAE_IS_OFFSET, pending);
axienet_iow(lp, XAE_IE_OFFSET, 0);
axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
axienet_iow(lp, XAE_FCC_OFFSET, fcc_reg);
axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
axienet_iow(lp, XAE_UAW0_OFFSET,
axienet_iow(lp, XAE_UAW1_OFFSET,
axienet_iow(lp, XAE_FMI_OFFSET, reg);
axienet_iow(lp, XAE_FMI_OFFSET, reg);
axienet_iow(lp, XAE_AF0_OFFSET, 1); /* Multicast bit */
axienet_iow(lp, XAE_AF1_OFFSET, 0);
axienet_iow(lp, XAE_AM0_OFFSET, 1); /* ditto */
axienet_iow(lp, XAE_AM1_OFFSET, 0);
axienet_iow(lp, XAE_FFE_OFFSET, 1);
axienet_iow(lp, XAE_FMI_OFFSET, reg);
axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
axienet_iow(lp, XAE_AM0_OFFSET, 0xffffffff);
axienet_iow(lp, XAE_AM1_OFFSET, 0x0000ffff);
axienet_iow(lp, XAE_FFE_OFFSET, 1);
axienet_iow(lp, XAE_FMI_OFFSET, reg);
axienet_iow(lp, XAE_FFE_OFFSET, 0);
axienet_iow(lp, tp->reg, reg);
axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ?
axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
axienet_iow(lp, XAE_MDIO_MC_OFFSET,
axienet_iow(lp, XAE_MDIO_MC_OFFSET,
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,