axienet_dma_out32
axienet_dma_out32(lp, reg, lower_32_bits(addr));
axienet_dma_out32(lp, reg, lower_32_bits(addr));
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, lp->tx_dma_cr);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);