ax_spi_read
ctrl_reg = ax_spi_read(xspi, AX_SPI_CR2);
new_ctrl_reg = ax_spi_read(xspi, AX_SPI_CR1);
if (ax_spi_read(xspi, AX_SPI_IVR) & AX_SPI_IVR_TFOV)
xspi->current_rx_fifo_word_for_irq = ax_spi_read(xspi, AX_SPI_RXFIFO);
u32 avail_bytes = ax_spi_read(xspi, AX_SPI_RX_FBCAR);
while (ax_spi_read(xspi, AX_SPI_RX_FBCAR) > 0 && safety_words-- > 0)
ax_spi_read(xspi, AX_SPI_RXFIFO);
intr_status = ax_spi_read(xspi, AX_SPI_IVR);
while (ax_spi_read(xspi, AX_SPI_RX_FBCAR) > 0 && drain_limit-- > 0)
ax_spi_read(xspi, AX_SPI_RXFIFO); // Read and discard
reg_value = ax_spi_read(xspi, AX_SPI_CR1);
reg_value = ax_spi_read(xspi, AX_SPI_CR1);
xspi->current_rx_fifo_word = ax_spi_read(xspi, AX_SPI_RXFIFO);
reg_val = ax_spi_read(xspi, AX_SPI_CR2);
reg_val = ax_spi_read(xspi, AX_SPI_CR2);
u32 tx_count_reg = ax_spi_read(xspi, AX_SPI_TX_FBCAR);
rx_count_reg = ax_spi_read(xspi, AX_SPI_RX_FBCAR);
u32 tx_fifo_level = ax_spi_read(xspi, AX_SPI_TX_FBCAR);
reg_value = ax_spi_read(xspi, AX_SPI_CR1);
reg_value = ax_spi_read(xspi, AX_SPI_CR2);