arch/powerpc/perf/generic-compat-pmu.c

109

CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);

arch/powerpc/perf/generic-compat-pmu.c

110

CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);

arch/powerpc/perf/generic-compat-pmu.c

111

CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);

arch/powerpc/perf/generic-compat-pmu.c

112

CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);

arch/powerpc/perf/generic-compat-pmu.c

113

CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);

arch/powerpc/perf/generic-compat-pmu.c

114

CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);

arch/powerpc/perf/generic-compat-pmu.c

115

CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);

arch/powerpc/perf/power10-pmu.c

133

CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);

arch/powerpc/perf/power10-pmu.c

134

CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);

arch/powerpc/perf/power10-pmu.c

135

CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);

arch/powerpc/perf/power10-pmu.c

136

CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);

arch/powerpc/perf/power10-pmu.c

137

CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);

arch/powerpc/perf/power10-pmu.c

138

CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);

arch/powerpc/perf/power10-pmu.c

139

CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);

arch/powerpc/perf/power10-pmu.c

140

CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);

arch/powerpc/perf/power10-pmu.c

141

CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);

arch/powerpc/perf/power10-pmu.c

142

CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3);

arch/powerpc/perf/power10-pmu.c

143

CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);

arch/powerpc/perf/power10-pmu.c

144

CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);

arch/powerpc/perf/power10-pmu.c

145

CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);

arch/powerpc/perf/power10-pmu.c

146

CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);

arch/powerpc/perf/power10-pmu.c

147

CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);

arch/powerpc/perf/power10-pmu.c

148

CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);

arch/powerpc/perf/power8-pmu.c

133

CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);

arch/powerpc/perf/power8-pmu.c

134

CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);

arch/powerpc/perf/power8-pmu.c

136

CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);

arch/powerpc/perf/power8-pmu.c

137

CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);

arch/powerpc/perf/power8-pmu.c

138

CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);

arch/powerpc/perf/power8-pmu.c

139

CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);

arch/powerpc/perf/power8-pmu.c

140

CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);

arch/powerpc/perf/power8-pmu.c

142

CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);

arch/powerpc/perf/power8-pmu.c

143

CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);

arch/powerpc/perf/power8-pmu.c

144

CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);

arch/powerpc/perf/power8-pmu.c

145

CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);

arch/powerpc/perf/power8-pmu.c

146

CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);

arch/powerpc/perf/power8-pmu.c

148

CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);

arch/powerpc/perf/power8-pmu.c

149

CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);

arch/powerpc/perf/power8-pmu.c

150

CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);

arch/powerpc/perf/power8-pmu.c

151

CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);

arch/powerpc/perf/power9-pmu.c

177

CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);

arch/powerpc/perf/power9-pmu.c

178

CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);

arch/powerpc/perf/power9-pmu.c

179

CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);

arch/powerpc/perf/power9-pmu.c

180

CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);

arch/powerpc/perf/power9-pmu.c

181

CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);

arch/powerpc/perf/power9-pmu.c

182

CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);

arch/powerpc/perf/power9-pmu.c

183

CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);

arch/powerpc/perf/power9-pmu.c

184

CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);

arch/powerpc/perf/power9-pmu.c

185

CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);

arch/powerpc/perf/power9-pmu.c

186

CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);

arch/powerpc/perf/power9-pmu.c

187

CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);

arch/powerpc/perf/power9-pmu.c

188

CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);

arch/powerpc/perf/power9-pmu.c

189

CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);

arch/powerpc/perf/power9-pmu.c

190

CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);