drivers/gpu/drm/i915/display/intel_dsb.c

200

!IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES));

drivers/gpu/drm/i915/display/intel_dsb.c

521

aligned_tail = ALIGN(tail, CACHELINE_BYTES);

drivers/gpu/drm/i915/display/intel_dsb.c

537

aligned_tail = ALIGN(tail, CACHELINE_BYTES);

drivers/gpu/drm/i915/display/intel_dsb.c

984

size = ALIGN(max_cmds * 8, CACHELINE_BYTES);

drivers/gpu/drm/i915/gt/intel_engine.h

33

#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))

drivers/gpu/drm/i915/gt/intel_lrc.c

1476

while ((unsigned long)cs % CACHELINE_BYTES)

drivers/gpu/drm/i915/gt/intel_lrc.c

1702

while ((unsigned long)batch % CACHELINE_BYTES)

drivers/gpu/drm/i915/gt/intel_lrc.c

1799

while ((unsigned long)batch % CACHELINE_BYTES)

drivers/gpu/drm/i915/gt/intel_lrc.c

1901

CACHELINE_BYTES))) {

drivers/gpu/drm/i915/gt/intel_lrc.c

808

GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES));

drivers/gpu/drm/i915/gt/intel_lrc.c

811

ctx_bb_ggtt_addr | (size / CACHELINE_BYTES);

drivers/gpu/drm/i915/gt/intel_ring.c

170

ring->effective_size -= 2 * CACHELINE_BYTES;

drivers/gpu/drm/i915/gt/intel_ring.h

110

#define cacheline(a) round_down(a, CACHELINE_BYTES)

drivers/gpu/drm/i915/gt/intel_ring.h

138

return (head - tail - CACHELINE_BYTES) & (size - 1);

drivers/gpu/drm/i915/gt/intel_ring_types.h

20

#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

431

u8 unused[CACHELINE_BYTES - sizeof(u32)];

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

467

BUILD_BUG_ON(sizeof(struct sync_semaphore) != CACHELINE_BYTES);

drivers/gpu/drm/i915/gvt/cmd_parser.c

2900

ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,

drivers/gpu/drm/i915/gvt/cmd_parser.c

3018

roundup(ctx_size + CACHELINE_BYTES,

drivers/gpu/drm/i915/gvt/cmd_parser.c

3073

memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);

drivers/gpu/drm/i915/gvt/scheduler.c

1722

CACHELINE_BYTES;

drivers/gpu/drm/i915/gvt/scheduler.c

1741

CACHELINE_BYTES)) {

drivers/gpu/drm/i915/gvt/scheduler.c

632

0, CACHELINE_BYTES, 0);

drivers/gpu/drm/i915/gvt/scheduler.c

653

memset(per_ctx_va, 0, CACHELINE_BYTES);

drivers/gpu/drm/xe/xe_guc_submit_types.h

40

u8 unused[CACHELINE_BYTES - sizeof(u32)];