bcm_qspi_read
u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
val = bcm_qspi_read(qspi, MSPI, offset);
msb = bcm_qspi_read(qspi, MSPI, msb_offset);
lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));