C5
/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
static const u64 C5[256] = {
C5[(int)(K[3] >> 16) & 0xff] ^
C5[(int)(K[4] >> 16) & 0xff] ^
C5[(int)(K[5] >> 16) & 0xff] ^
C5[(int)(K[6] >> 16) & 0xff] ^
C5[(int)(K[7] >> 16) & 0xff] ^
C5[(int)(K[0] >> 16) & 0xff] ^
C5[(int)(K[1] >> 16) & 0xff] ^
C5[(int)(K[2] >> 16) & 0xff] ^
C5[(int)(state[3] >> 16) & 0xff] ^
C5[(int)(state[4] >> 16) & 0xff] ^
C5[(int)(state[5] >> 16) & 0xff] ^
C5[(int)(state[6] >> 16) & 0xff] ^
C5[(int)(state[7] >> 16) & 0xff] ^
C5[(int)(state[0] >> 16) & 0xff] ^
C5[(int)(state[1] >> 16) & 0xff] ^
C5[(int)(state[2] >> 16) & 0xff] ^
FUNC_GROUP_DECL(I2C9, C5, B4);
ASPEED_PINCTRL_PIN(C5),
SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
FUNC_GROUP_DECL(TIMER5, C5);
SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
ASPEED_PINCTRL_PIN(C5),
SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4),
PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2);
FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
ASPEED_PINCTRL_PIN(C5),