b43_radio_set
void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
b43_radio_set(dev, 0x51, 0x0004);
b43_radio_set(dev, 0x007A, 0x0050);
b43_radio_set(dev, 0x007A, 0x0020);
b43_radio_set(dev, 0x0051, 0x0004);
b43_radio_set(dev, 0x007A, 0x0007);
b43_radio_set(dev, 0x007A, 0x0020);
b43_radio_set(dev, 0x0051, 0x0004);
b43_radio_set(dev, 0x007A, 0x0070);
b43_radio_set(dev, 0x007A, 0x0080);
b43_radio_set(dev, 0x007A, 0x000F);
b43_radio_set(dev, 0x007A, 0x0070);
b43_radio_set(dev, 0x007A, 0x0080);
b43_radio_set(dev, 0x007A, 0x000F);
b43_radio_set(dev, 0xa, 0x60);
b43_radio_set(dev, routing[i] | 0x146, 0x3);
b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078);
b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080);
b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
b43_radio_set(dev, 0x8bf, 0x1);
b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4);
b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1);
b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1);
b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2);
b43_radio_set(dev, 0x004, 0x40);
b43_radio_set(dev, 0x120, 0x10);
b43_radio_set(dev, 0x078, 0x80);
b43_radio_set(dev, 0x129, 0x2);
b43_radio_set(dev, 0x057, 0x1);
b43_radio_set(dev, 0x05b, 0x2);
b43_radio_set(dev, 0x09b, 0xf0);
b43_radio_set(dev, 0x0f7, 0x4);
b43_radio_set(dev, 0x11f, 0x2);
b43_radio_set(dev, 0x007, 0x1);
b43_radio_set(dev, 0x0ff, 0x10);
b43_radio_set(dev, 0x11f, 0x4);
b43_radio_set(dev, 0x005, 0x8);
b43_radio_set(dev, 0x082, 0x20);
b43_radio_set(dev, 0x09d, 0x4);
b43_radio_set(dev, 0x044, 0x7);
b43_radio_set(dev, 0x12b, 0xe);
b43_radio_set(dev, 0x044, 0x0c);
b43_radio_set(dev, B2063_PA_SP1, 0x2);
b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
b43_radio_set(dev, B2063_PLL_SP1, 0x40);
b43_radio_set(dev, B2063_COMM15, 0x1E);
b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
b43_radio_set(dev, B2063_PLL_SP2, 0x3);
b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
b43_radio_set(dev, B2063_COMM8, 0x38);
b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2);
b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
b43_radio_set(dev, B2055_CAL_MISC, 0x1);
b43_radio_set(dev, B2055_CAL_MISC, 0x40);
b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
b43_radio_set(dev, 0x4f, 0x1);
b43_radio_set(dev, 0xd4, 0x1);
b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4);
b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01);
b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2);
b43_radio_set(dev, 0x7A, 0x0008);