C2
/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
static const u64 C2[256] = {
C2[(int)(K[6] >> 40) & 0xff] ^
C2[(int)(K[7] >> 40) & 0xff] ^
C2[(int)(K[0] >> 40) & 0xff] ^
C2[(int)(K[1] >> 40) & 0xff] ^
C2[(int)(K[2] >> 40) & 0xff] ^
C2[(int)(K[3] >> 40) & 0xff] ^
C2[(int)(K[4] >> 40) & 0xff] ^
C2[(int)(K[5] >> 40) & 0xff] ^
C2[(int)(state[6] >> 40) & 0xff] ^
C2[(int)(state[7] >> 40) & 0xff] ^
C2[(int)(state[0] >> 40) & 0xff] ^
C2[(int)(state[1] >> 40) & 0xff] ^
C2[(int)(state[2] >> 40) & 0xff] ^
C2[(int)(state[3] >> 40) & 0xff] ^
C2[(int)(state[4] >> 40) & 0xff] ^
C2[(int)(state[5] >> 40) & 0xff] ^
func(C2) \
func(C2) \
u16 C1, u16 C2, u16 C3, u16 C4)
adv7511_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
adv7511_wr(sd, 0x2B, C2);
sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
sdp_io_write(sd, 0xf3, c->C2);
IWL_MLD_ENC_EHT_RU(1_2_2, C2);
IWL_MVM_ENC_EHT_RU(1_2_2, C2);
SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC);
PIN_DECL_1(C2, GPIOQ1, SDA3);
FUNC_GROUP_DECL(I2C3, D3, C2);
ASPEED_PINCTRL_PIN(C2),
SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
ASPEED_PINCTRL_PIN(C2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13),
SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13),
PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN);
FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
ASPEED_PINCTRL_PIN(C2),
PIC32_PINCTRL_GROUP(34, C2,
u16 C2;