C1
/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
static const u64 C1[256] = {
C1[(int)(K[7] >> 48) & 0xff] ^
C1[(int)(K[0] >> 48) & 0xff] ^
C1[(int)(K[1] >> 48) & 0xff] ^
C1[(int)(K[2] >> 48) & 0xff] ^
C1[(int)(K[3] >> 48) & 0xff] ^
C1[(int)(K[4] >> 48) & 0xff] ^
C1[(int)(K[5] >> 48) & 0xff] ^
C1[(int)(K[6] >> 48) & 0xff] ^
C1[(int)(state[7] >> 48) & 0xff] ^
C1[(int)(state[0] >> 48) & 0xff] ^
C1[(int)(state[1] >> 48) & 0xff] ^
C1[(int)(state[2] >> 48) & 0xff] ^
C1[(int)(state[3] >> 48) & 0xff] ^
C1[(int)(state[4] >> 48) & 0xff] ^
C1[(int)(state[5] >> 48) & 0xff] ^
C1[(int)(state[6] >> 48) & 0xff] ^
func(C1) \
func(C1) \
u16 C1, u16 C2, u16 C3, u16 C4)
adv7511_wr_and_or(sd, 0x28, 0xe0, C1>>8);
adv7511_wr(sd, 0x29, C1);
sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
sdp_io_write(sd, 0xf1, c->C1);
IWL_MLD_ENC_EHT_RU(1_1_2, C1);
IWL_MVM_ENC_EHT_RU(1_1_2, C1);
ASPEED_PINCTRL_PIN(C1),
SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC);
PIN_DECL_1(C1, GPIOK2, SCL6);
FUNC_GROUP_DECL(I2C6, C1, F4);
SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
ASPEED_PINCTRL_PIN(C1),
SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14),
SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14),
PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0);
FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
ASPEED_PINCTRL_PIN(C1),
PIC32_PINCTRL_GROUP(33, C1,
u16 C1;
#define C4 C1 C1 C1 C1