ax_spi
*p = AX_READ(&ax_local->ax_spi, offset);
AX_WRITE(&ax_local->ax_spi, MDIOCR_RADDR(loc)
&ax_local->ax_spi, P2_MDIOCR);
ret = AX_READ(&ax_local->ax_spi, P2_MDIODR);
AX_WRITE(&ax_local->ax_spi, val, P2_MDIODR);
AX_WRITE(&ax_local->ax_spi,
&ax_local->ax_spi, P2_MDIOCR);
maccr |= AX_READ(&ax_local->ax_spi, P0_MACCR) &
AX_WRITE(&ax_local->ax_spi, maccr, P0_MACCR);
temp = AX_READ(&ax_local->ax_spi, P2_CRIR);
AX_WRITE(&ax_local->ax_spi, (AX_READ(&ax_local->ax_spi, P0_PSCR)
AX_WRITE(&ax_local->ax_spi,
AX_WRITE(&ax_local->ax_spi, rx_ctl, P2_RXCR);
AX_WRITE(&ax_local->ax_spi, ((u16)(ndev->dev_addr[4] << 8) |
AX_WRITE(&ax_local->ax_spi, ((u16)(ndev->dev_addr[2] << 8) |
AX_WRITE(&ax_local->ax_spi, ((u16)(ndev->dev_addr[0] << 8) |
temp = AX_READ(&ax_local->ax_spi, P3_MACASR0);
temp = AX_READ(&ax_local->ax_spi, P3_MACASR1);
temp = AX_READ(&ax_local->ax_spi, P3_MACASR2);
free_pages = AX_READ(&ax_local->ax_spi, P0_TFBFCR) & TX_FREEBUF_MASK;
tmp = AX_READ(&ax_local->ax_spi, P0_TFBFCR)
AX_WRITE(&ax_local->ax_spi, tmp | TFBFCR_TX_PAGE_SET |
u8 spi_len = ax_local->ax_spi.comp ? 1 : 4;
AX_WRITE(&ax_local->ax_spi,
axspi_write_txq(&ax_local->ax_spi, tx_skb->data, tx_skb->len);
if (((AX_READ(&ax_local->ax_spi, P0_TSNR) & TXNR_TXB_IDLE) == 0) ||
((ISR_TXERR & AX_READ(&ax_local->ax_spi, P0_ISR)) != 0)) {
AX_WRITE(&ax_local->ax_spi, ISR_TXERR, P0_ISR);
AX_WRITE(&ax_local->ax_spi, TXNR_TXB_REINIT |
AX_READ(&ax_local->ax_spi, P0_TSNR), P0_TSNR);
AX_WRITE(&ax_local->ax_spi, PSR_RESET, P0_PSR);
AX_WRITE(&ax_local->ax_spi, PSR_RESET_CLR, P0_PSR);
AX_WRITE(&ax_local->ax_spi, AX_READ(&ax_local->ax_spi, P0_RTWCR)
pkt_cnt = AX_READ(&ax_local->ax_spi, P0_RXBCR2) & RXBCR2_PKT_MASK;
pkt_len = AX_READ(&ax_local->ax_spi, P0_RCPHR) & 0x7FF;
AX_WRITE(&ax_local->ax_spi, RXBCR1_RXB_DISCARD, P0_RXBCR1);
&ax_local->ax_spi, P0_PSR);
AX_WRITE(&ax_local->ax_spi, RXBCR1_RXB_START | w_count, P0_RXBCR1);
axspi_read_rxq(&ax_local->ax_spi,
if ((AX_READ(&ax_local->ax_spi, P0_RXBCR2) & RXBCR2_RXB_IDLE) == 0) {
AX_WRITE(&ax_local->ax_spi, RXBCR2_RXB_REINIT, P0_RXBCR2);
AX_WRITE(&ax_local->ax_spi, ISR_RXPKT, P0_ISR);
isr = AX_READ(&ax_local->ax_spi, P0_ISR);
AX_WRITE(&ax_local->ax_spi, isr, P0_ISR);
temp = AX_READ(&ax_local->ax_spi, P4_SPICR);
AX_WRITE(&ax_local->ax_spi, TXNR_TXB_REINIT, P0_TSNR);
AX_WRITE(&ax_local->ax_spi,
ax_local->ax_spi.comp = 1;
AX_WRITE(&ax_local->ax_spi,
AX_WRITE(&ax_local->ax_spi, IMR_MASKALL, P0_IMR);
AX_WRITE(&ax_local->ax_spi, IMR_DEFAULT, P0_IMR);
ax_local->ax_spi.comp = 0;
maccr |= AX_READ(&ax_local->ax_spi, P0_MACCR) &
AX_WRITE(&ax_local->ax_spi, maccr, P0_MACCR);
AX_WRITE(&ax_local->ax_spi, EECR_RELOAD, P3_EECR);
AX_WRITE(&ax_local->ax_spi, COERCR0_DEFAULT, P4_COERCR0);
AX_WRITE(&ax_local->ax_spi, COERCR1_DEFAULT, P4_COERCR1);
AX_WRITE(&ax_local->ax_spi, 0, P4_COERCR0);
AX_WRITE(&ax_local->ax_spi, 0, P4_COERCR1);
AX_WRITE(&ax_local->ax_spi, COETCR0_DEFAULT, P4_COETCR0);
AX_WRITE(&ax_local->ax_spi, COETCR1_TXPPPE, P4_COETCR1);
AX_WRITE(&ax_local->ax_spi, 0, P4_COETCR0);
AX_WRITE(&ax_local->ax_spi, 0, P4_COETCR1);
&ax_local->ax_spi, P0_PSR);
t = AX_READ(&ax_local->ax_spi, P1_RXBSPCR);
AX_WRITE(&ax_local->ax_spi, t, P1_RXBSPCR);
AX_WRITE(&ax_local->ax_spi, RPPER_RXEN, P1_RPPER);
t = AX_READ(&ax_local->ax_spi, P0_FER);
AX_WRITE(&ax_local->ax_spi, t, P0_FER);
AX_WRITE(&ax_local->ax_spi,
AX_WRITE(&ax_local->ax_spi,
(AX_READ(&ax_local->ax_spi, P2_LCR1) & LCR_LED2_MASK) |
AX_WRITE(&ax_local->ax_spi, PCR_PHYID(AX88796C_PHY_ID), P2_PCR);
AX_WRITE(&ax_local->ax_spi, IMR_DEFAULT, P0_IMR);
spi_message_init(&ax_local->ax_spi.rx_msg);
AX_WRITE(&ax_local->ax_spi, IMR_MASKALL, P0_IMR);
ax_local->ax_spi.spi = spi;
struct axspi_data ax_spi;
int axspi_write_reg(struct axspi_data *ax_spi, u8 reg, u16 value)
memset(ax_spi->cmd_buf, 0, sizeof(ax_spi->cmd_buf));
ax_spi->cmd_buf[0] = AX_SPICMD_WRITE_REG; /* OP code read register */
ax_spi->cmd_buf[1] = reg; /* register address */
ax_spi->cmd_buf[2] = value;
ax_spi->cmd_buf[3] = value >> 8;
ret = spi_write(ax_spi->spi, ax_spi->cmd_buf, 4);
dev_err(&ax_spi->spi->dev, "%s() failed: ret = %d\n", __func__, ret);
int axspi_wakeup(struct axspi_data *ax_spi)
ax_spi->cmd_buf[0] = AX_SPICMD_EXIT_PWD; /* OP */
ret = spi_write(ax_spi->spi, ax_spi->cmd_buf, 1);
dev_err(&ax_spi->spi->dev, "%s() failed: ret = %d\n", __func__, ret);
int axspi_read_status(struct axspi_data *ax_spi, struct spi_status *status)
ax_spi->cmd_buf[0] = AX_SPICMD_READ_STATUS;
ret = spi_write_then_read(ax_spi->spi, ax_spi->cmd_buf, 1, (u8 *)status, 3);
dev_err(&ax_spi->spi->dev, "%s() failed: ret = %d\n", __func__, ret);
int axspi_read_rxq(struct axspi_data *ax_spi, void *data, int len)
struct spi_transfer *xfer = ax_spi->spi_rx_xfer;
memcpy(ax_spi->cmd_buf, ax88796c_rx_cmd_buf, 5);
xfer->tx_buf = ax_spi->cmd_buf;
xfer->len = ax_spi->comp ? 2 : 5;
spi_message_add_tail(xfer, &ax_spi->rx_msg);
spi_message_add_tail(xfer, &ax_spi->rx_msg);
ret = spi_sync(ax_spi->spi, &ax_spi->rx_msg);
dev_err(&ax_spi->spi->dev, "%s() failed: ret = %d\n", __func__, ret);
int axspi_write_txq(const struct axspi_data *ax_spi, void *data, int len)
return spi_write(ax_spi->spi, data, len);
u16 axspi_read_reg(struct axspi_data *ax_spi, u8 reg)
int len = ax_spi->comp ? 3 : 4;
ax_spi->cmd_buf[0] = 0x03; /* OP code read register */
ax_spi->cmd_buf[1] = reg; /* register address */
ax_spi->cmd_buf[2] = 0xFF; /* dumy cycle */
ax_spi->cmd_buf[3] = 0xFF; /* dumy cycle */
ret = spi_write_then_read(ax_spi->spi,
ax_spi->cmd_buf, len,
ax_spi->rx_buf, 2);
dev_err(&ax_spi->spi->dev,
le16_to_cpus((u16 *)ax_spi->rx_buf);
return *(u16 *)ax_spi->rx_buf;
int axspi_read_rxq(struct axspi_data *ax_spi, void *data, int len);
int axspi_write_txq(const struct axspi_data *ax_spi, void *data, int len);
u16 axspi_read_reg(struct axspi_data *ax_spi, u8 reg);
int axspi_write_reg(struct axspi_data *ax_spi, u8 reg, u16 value);
int axspi_read_status(struct axspi_data *ax_spi, struct spi_status *status);
int axspi_wakeup(struct axspi_data *ax_spi);
static inline u16 AX_READ(struct axspi_data *ax_spi, u8 offset)
return axspi_read_reg(ax_spi, offset);
static inline int AX_WRITE(struct axspi_data *ax_spi, u16 value, u8 offset)
return axspi_write_reg(ax_spi, offset, value);
static inline int AX_READ_STATUS(struct axspi_data *ax_spi,
return axspi_read_status(ax_spi, status);
static inline int AX_WAKEUP(struct axspi_data *ax_spi)
return axspi_wakeup(ax_spi);
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
static void ax_spi_fill_tx_fifo(struct ax_spi *xspi)
static u8 ax_spi_get_rx_byte_for_irq(struct ax_spi *xspi)
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
static inline u32 ax_spi_read(struct ax_spi *xspi, u32 offset)
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
static inline void ax_spi_write(struct ax_spi *xspi, u32 offset, u32 val)
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
static void ax_spi_detect_fifo_depth(struct ax_spi *xspi)
static inline void ax_spi_write_b(struct ax_spi *xspi, u32 offset, u8 val)
static u8 ax_spi_get_rx_byte(struct ax_spi *xspi)
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
static void ax_spi_init_hw(struct ax_spi *xspi)
struct ax_spi *xspi = spi_controller_get_devdata(spi->controller);
struct ax_spi *xspi;
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);
struct ax_spi *xspi = spi_controller_get_devdata(ctlr);