ath12k_hif_write32
ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, addr, val);
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr);
ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_base_msb_offset(hal),
ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_id_offset(hal), val);
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base, 0);
ath12k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, 0);
ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_misc_offset(hal),
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base +
ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr);
ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(hal), val);
ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(hal), val);
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, reg_base, 0);
ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(hal), val);
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_WBM_REG +
ath12k_hif_write32(ab,
ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id,
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(hal),
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(hal),
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(hal), cmem_base);
ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(hal), val);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(hal), val);
ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(hal),
ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(hal),
ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(hal),
ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(hal),
ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
ath12k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +