ath11k_pcic_read32
.read32 = ath11k_pcic_read32,
val = ath11k_pcic_read32(ab, MHISTATUS);
sub_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_SUB_VER);
val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
v = ath11k_pcic_read32(ab, offset);
v = ath11k_pcic_read32(ab, offset);
val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
.read32 = ath11k_pcic_read32,
soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
EXPORT_SYMBOL(ath11k_pcic_read32);
u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset);