ath11k_hif_write32
ath11k_hif_write32(ab, addr, val);
ath11k_hif_write32(ab, reg_base +
ath11k_hif_write32(ab, reg_base +
ath11k_hif_write32(ab,
ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val);
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val);
ath11k_hif_write32(ab,
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab),
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab),
ath11k_hif_write32(ab, reg_base, 0);
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0);
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val);
ath11k_hif_write32(ab, reg_base +
ath11k_hif_write32(ab, reg_base +
ath11k_hif_write32(ab, reg_base +
ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val);
ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val);
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab, reg_base, 0);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val);
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab,
ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,