au8522_writereg
return au8522_writereg(state, 0x8000 |
ret = au8522_writereg(state, 0x8000 |
au8522_writereg(state, 0xa4, 1 << 5);
au8522_writereg(state, 0xa4, 1 << 5);
EXPORT_SYMBOL(au8522_writereg);
return au8522_writereg(state, 0x106, 1);
return au8522_writereg(state, 0x106, 0);
return au8522_writereg(state, 0x106, 1);
return au8522_writereg(state, 0x106, 0);
au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
au8522_writereg(state, filter_coef[i].reg_name,
au8522_writereg(state, AU8522_REG42EH, 0x87);
au8522_writereg(state, AU8522_REG42FH, 0xa2);
au8522_writereg(state, AU8522_REG430H, 0xbf);
au8522_writereg(state, AU8522_REG431H, 0xcb);
au8522_writereg(state, AU8522_REG432H, 0xa1);
au8522_writereg(state, AU8522_REG433H, 0x41);
au8522_writereg(state, AU8522_REG434H, 0x88);
au8522_writereg(state, AU8522_REG435H, 0xc2);
au8522_writereg(state, AU8522_REG436H, 0x3c);
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, lpfilter_coef[i].reg_name,
au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
au8522_writereg(state, reg->reg, reg->val & 0xff);
au8522_writereg(state, 0xa4, 1 << 5);
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
au8522_writereg(state, 0x106, 1);
au8522_writereg(state, 0x00b5, r0b5);
au8522_writereg(state, 0x00b6, r0b6);
au8522_writereg(state, 0x00b7, r0b7);
au8522_writereg(state,
au8522_writereg(state,
au8522_writereg(state,
au8522_writereg(state, 0x821a, 0x00);
au8522_writereg(state,
int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);