aty_ld_le32
aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
reg = aty_ld_le32(LVDS_GEN_CNTL);
reg = aty_ld_le32(LVDS_GEN_CNTL);
aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
config = aty_ld_le32(CNFG_CNTL) & ~3;
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
aty_ld_le32(LVDS_GEN_CNTL);
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
aty_ld_le32(LVDS_GEN_CNTL);
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
dac = aty_ld_le32(DAC_CNTL);
aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
return aty_ld_le32(CLOCK_CNTL_DATA);
val = aty_ld_le32(BIOS_0_SCRATCH);
if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
aty_ld_le32(GEN_RESET_CNTL);
aty_ld_le32(GEN_RESET_CNTL);
temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
switch (aty_ld_le32(MEM_CNTL) & 0x3) {
fifo_space = 16 - fls(aty_ld_le32(FIFO_STAT, par) & 0xffff);
while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
pr_cont(" %08X", aty_ld_le32(i, par));
temp = aty_ld_le32(LCD_INDEX, par);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
return aty_ld_le32(lt_lcd_regs[index], par);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
temp = aty_ld_le32(LCD_INDEX, par);
return aty_ld_le32(LCD_DATA, par);
aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
stat0 = aty_ld_le32(CNFG_STAT0, par);
par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
aty_ld_le32(BUS_CNTL, par),
aty_ld_le32(DAC_CNTL, par),
aty_ld_le32(MEM_CNTL, par),
aty_ld_le32(EXT_MEM_CNTL, par),
aty_ld_le32(CRTC_GEN_CNTL, par),
aty_ld_le32(DSP_CONFIG, par),
aty_ld_le32(DSP_ON_OFF, par),
aty_ld_le32(CLOCK_CNTL, par));
aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) |
gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
mem = aty_ld_le32(MEM_CNTL, par);
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
clock_r = aty_ld_le32(CLOCK_CNTL, par);
switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
i = aty_ld_le32(GP_IO, par); /* get primary sense value */
i = aty_ld_le32(GP_IO, par);
i = aty_ld_le32(GP_IO, par);
sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
aty_ld_le32(LCD_INDEX, par);
u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
aty_st_le32(CRTC_INT_CNTL, aty_ld_le32(CRTC_INT_CNTL, par) & ~0x20,
aty_ld_le32(GEN_TEST_CNTL, par) &
aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par);
aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par);
crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
memcntl = aty_ld_le32(MEM_CNTL, par);
dsp_config = aty_ld_le32(DSP_CONFIG, par);
aty_ld_le32(DSP_ON_OFF, par);
aty_ld_le32(VGA_DSP_CONFIG, par);
aty_ld_le32(VGA_DSP_ON_OFF, par);
aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par)
aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par)