ath10k_pci_soc_read32
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);