arch/mips/ath79/clock.c

157

t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);

arch/mips/ath79/clock.c

245

bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);

arch/mips/ath79/clock.c

360

bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);

arch/mips/ath79/clock.c

443

bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);

arch/mips/ath79/clock.c

532

misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);

arch/mips/ath79/clock.c

536

bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);

arch/mips/ath79/common.c

113

t = ath79_reset_rr(reg);

arch/mips/ath79/common.c

145

t = ath79_reset_rr(reg);

arch/mips/ath79/setup.c

52

id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);

arch/mips/pci/pci-ar724x.c

419

if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)